The present invention relates in general to cache memory controllers, and, in particular, to a cache memory controller capable of servicing pipelined memory accesses issued by a processor.
The use of a cache memory in association with a processor has become increasingly popular. Typically, a relatively small, high speed cache memory, constructed, for example, from Static Random Access Memory (SPRAM), is used in association with a larger, slower main memory, employing, for example, Dynamic Random Access Memory (DRAM). The cache memory stores a subset of the contents of the main memory --typically corresponding to the most recently accessed storage locations within the main memory.
Recently, microprocessors have been introduced which are capable of issuing pipelined memory accesses, or memory requests. An example of such a microprocessor is the P5, or PENTIUM-brand processor from Intel Corp. These processors are capable of initiating a second external memory request prior to the completion of the servicing of a first external memory request.
In general, each memory request requires several system clock cycles to be fully serviced, or completed. During a first clock cycle, a valid memory address is issued by the processor, along with control signals indicating address validity and defining the nature (i.e., read vs. write, memory vs. input/output) of the present bus cycle. Next, the cache controller will determine whether the requested data is present within cache memory. If so, (i.e., a cache read hit has occurred), the requested data will be quickly made available to the processor. If not, the requested data must be retrieved from slower main memory. In either event, a latency of at least several clock cycles typically transpires between the time the processor outputs a valid address onto its address bus and the time the requested data is presented to the processor on its data bus.
Pipelining is an attempt to make use of this latency period, by filling this otherwise "dead" time on the data bus with data associated with a first memory request which is overlapping in time with a second memory request. As a result, pipelining memory accesses results in increased system throughput, since the data bus remains idle for fewer bus cycles.
Accordingly, it is an object of the present invention to provide a cache controller capable of servicing multiple, pipelined multi-byte read requests issued by a processor to a cache memory.
It is another object of the present invention to provide a cache controller capable of bursting multiple, pipelined multi-byte read requests issued by a processor, so that servicing of a second pipelined multi-word bursted read memory request overlaps in time with the servicing of a first pipelined multi-word bursted read memory request.
These and other objects and features of the present invention will become apparent in light of the present specification, drawings and claims.